Capture your sourced parts as nets and power in KiCad.
Read this once. You won't open KiCad yet. It's the map for everything you're about to wire. As you go: Do · = do it in KiCad, Check = a quick gut-check, Eyeball it = verify by eye.
Think of the schematic as eight small jobs standing between a bare ESP32 module and a board you can plug in and flash. The board needs:
Each section below takes one of those jobs and shows you the exact parts that solve it, and the roadmap right below lists all eight in build order. Read them in order: they follow the power as it comes in at the USB connector and works its way to the chip. Every part has a (U1, C5, R3), the short label that ties its symbol, its BOM line, and its spot on the board together. You'll meet them in the tables under each section.
drag to rotate
| Island | What it does |
|---|---|
| 1 · Regulator (U2) | 5 V in → a steady 3.3 V rail |
| 2 · Decoupling & the module | caps right at U1's pins so the rail stays steady |
| 3 · Boot & reset | pull-ups + the EN / BOOT buttons |
| 4 · USB power & protection | the CC sink, the fuse, ESD at the port |
| 5 · USB data | the D+/D− pair to the module, named as a diff pair |
| 6 · Indicator LEDs | a power light + a user light, each current-limited |
| 7 · Headers & test points | every GPIO out to the breadboard |
| 8 · Grounds & no-connects | one ground net; flag every open pin |
These lessons run in KiCad 10: every menu path, shortcut, and dialog here matches version 10. If it isn't installed, grab KiCad 10 or newer first (it's free, official, and runs on Windows, macOS, and Linux). Already have it open? Skip straight to the starter download below.
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Arrange the parts the export gave you so the drawing reads the way the circuit works: power in at the top, signal flowing left to right.
Drag each part so the sheet reads left → right: inputs on the left, outputs on the right. Put (+3V3,
Each sub-circuit is one island: meet it, wire it, then eyeball it against the reference. Hold the full for the very end. Run it per-island and it's just a wall of 'not connected' noise.
One ordering habit saves the most rework: on each island, drop every power port and net label onto its pin first, then draw the few real wires between legs. Run a wire first and a label dropped on top of it later forces you to nudge the wire aside; place the labels first and the wires slot into clean space. Most connections here are by name anyway (same label = same net), so a drawn wire is the exception, not the rule.
the KiCad 10 keys you'll use
A handful of keys do most of the work: hover over a part and press the key. (Live list: Preferences → Hotkeys, or press ? in the editor.)
| Key | What it does |
|---|---|
| A | Add a symbol (place a part) |
| P | Add a power port: +3V3, +5V, GND, VBUS |
| W | Draw a wire |
| L | Place a net label |
| R / M / G | Rotate / move / drag (G keeps wires attached) |
| X / Y | Mirror across the X / Y axis |
| E / V / U | Edit properties / value / reference |
| Q | No-connect flag: mark a pin you leave open |
One more shortcut for the header slog: Insert repeats the last wire or label one grid-step down and auto-increments the trailing number (IO4→IO5→IO6…). Set the step under Preferences ▸ Schematic Editor ▸ Editing Options ▸ Label increment. The header order jumps around a lot, so Insert only earns its keep on the few unbroken runs (like IO4→IO7 or IO15→IO18). Everywhere else you place by hand from the table, and that's expected, not you doing it wrong. No Insert key (some compact laptops omit it)? Use the on-screen keyboard, or remap a key to Insert with Microsoft PowerToys ▸ Keyboard Manager. On a Mac it's Fn+Enter.
Connect with names, not a maze of lines. Two wires with the same label are the same connection.
For anything that crosses the sheet (a power rail, a reset line), give the wire a instead of dragging a line all the way across: two wires that share a label are connected, and the drawing stays clean. Use for +3V3 and GND so every part taps the rail by name. And remember that wires which merely cross aren't joined unless there's a junction dot: let KiCad drop those at real T-connections.
A power symbol (press P) is for a rail, a power/ground net lots of parts tap: VBUS, +5V, +3V3, GND. A net label (press L) is for a signal between a few pins: USB_D+, a reset line. The test: is it a rail many things share, or a signal between a few pins? Rail → power symbol; signal → net label. One mechanical difference: a power symbol drops straight onto the pin, but a net label rides a wire. So for a signal like EN, IO0, or IO2, draw a short wire off the pin first, then press L and drop the label on that wire. Dropped in open space it floats unattached (ERC flags it); dropped on the wire, the net takes the name. Note GND is a power symbol, not a label, the odd one out visually (the down-pointing triangle), but it behaves like +3V3 and VBUS: a global net every matching symbol joins by name.
First, the thing nobody tells you outright: you wire by pin name, not pin number. Your chips, the module, and the connector label their pins by name: the regulator's pins read VIN, VOUT, GND, EN; the module's read 3V3, EN, IO0, IO19, IO20. So when a step says 'U2's EN to VIN,' you find the pin named EN and wire it to the pin named VIN. (The little resistors and caps are the exception: they just show pins 1 and 2; that's fine, and there's a heads-up on exactly what every symbol looks like right before you download.) The names in this lesson are the names on those symbols. For the chips, 'which pin?' is answered by reading the part in front of you.
Your ESP32-S3 wants a clean 3.3 V supply, but USB gives you 5 V. Something has to step it down.
That something is U2, the RT9080. It's an , short for low-, which is just a voltage regulator that holds its output steady even when the input is only a little above it. Why not a simple voltage divider (two resistors)? Because a divider sags the moment the chip pulls current, and the ESP32's draw jumps every time its radio transmits. A regulator actively holds 3.3 V no matter the load. That's the whole point of a regulator. One thing to remember: the RT9080 needs a capacitor on its input and another on its output to stay stable: that's C5 and C6, 1 µF each. The datasheet promises stability with 1 µF ceramic in and out, which is exactly what we gave it.
| Ref | Part | Role |
|---|---|---|
| U2 | RT9080-33GJ5 | 5 V → 3.3 V LDO, 600 mA |
| C5 C6 | 1 µF X7R | LDO input / output stability caps |
This first one we do slowly together: every island after is the same handful of moves. Ctrl+F to U2 (it's already on the sheet, drawn as an AP2112K, that's expected, it's the RT9080), drag it to clear space, and wire it: U2 and its two caps.
A steady rail at the regulator is not the same as a steady rail at the chip a few centimetres away.
When the ESP32 switches its transistors millions of times a second, it grabs tiny gulps of current faster than the regulator across the board can possibly respond. Left unfed, the 3.3 V right at the chip's pins would dip on every gulp, and a fed a dipping rail glitches or resets. The fix is a small parked right at each power pin: C2 and C3 (0.1 µF each). They hold a little reserve of charge and hand it over instantly when the chip asks, then refill between demands. C1 (10 µF) plays the same game one size up: a for the whole 3.3 V rail, smoothing the larger swings the little caps don't cover. Together they're called bulk plus bypass.
| Ref | Part | Role |
|---|---|---|
| C2 C3 | 0.1 µF X7R | Bypass: clustered at the module's 3V3 pin |
| C1 | 10 µF X5R | Bulk reservoir for the rail |
Caps first, right at U1's power pins, then connect the module itself.
A digital input wired to nothing doesn't read 0. It floats. It picks up noise and reads randomly.
The ESP32 checks two the instant it wakes up: EN (chip-enable / reset) and GPIO0 (boot select). Both have to be at a definite level at that moment, so each gets a , R1 and R2, 10 kΩ, gently tying it to 3.3 V (logic high). EN high means the chip runs; GPIO0 high at reset means boot normally from flash. The two buttons override that resting level while you hold them. SW1 pulls EN to ground to reset the chip; holding SW2 (GPIO0 to ground) through a reset drops the chip into USB download mode so you can flash new firmware. The resistor sets the default; the button wins while it's pressed. One more part rides on EN: a cap, C7 (1 µF), from the EN net to GND. With R1's 10 kΩ it makes a ~10 ms RC delay: EN charges through R1 and only crosses 'high' well after the 3.3 V rail has settled, so the chip leaves reset cleanly instead of racing the supply. It also debounces SW1: a bare button's contact bounces, and without the cap one press can fire several resets. This is the CHIP_PU RC Espressif's ESP32-S3 design guide calls for; 1 µF is the more-generous value it suggests, for extra reset margin.
| Ref | Part | Role |
|---|---|---|
| R1 R2 |
The port that touches the outside world: tell the charger to send power, fuse the rail, and clamp static at the door.
Your board announces itself as a consumer, a , by tying each to ground through a 5.1 kΩ resistor, called . The host sees that exact resistance and only then switches on. There are two of them, R3 and R4, because Type-C is reversible: whichever way the plug goes in, one of CC1/CC2 is the live one, so both need their own Rd. These are (to ground), the mirror image of the boot pull-ups you just met. And 5.1 kΩ is the value the USB-C spec assigns to a basic sink.
| Ref | Part | Role |
|---|---|---|
| R3 R4 | 5.1 kΩ | CC1 / CC2 sink resistors (Rd) to GND |
It gets two guardians. F1 is a (a PTC polyfuse) on : if something downstream pulls too much current, it heats up, its resistance shoots up, and it throttles the current down to a trickle. Then, once it cools off, it returns to normal all by itself. It's a symmetric 2-pin part: either leg to , the other to +5V, no 'right way round.' That rename is deliberate: the connector side is VBUS
Two fixed pins, one , and a naming trick that pays off in LAYOUT.
The module talks USB on two fixed pins: D− is IO19, D+ is IO20, always (that's the name on the symbol). No other pins work, and nothing on the schematic hints at it. So the connector's two data lines run to exactly those pins, and pass through D1 on the way to clamp static.
Older ESP32 boards needed a separate USB-to-UART bridge (a CP2102 or CH340) just to flash and print to the serial monitor, because the classic ESP32 had no USB of its own. The ESP32-S3 does: a built-in USB-Serial-JTAG peripheral wired to exactly these two pins (IO19 = D−, IO20 = D+). So the USB-C port talks to the chip directly, and flashing, the serial console, and JTAG debug all run over the one cable: no bridge chip, no driver install. That's why this board's parts list has no CP2102 or CH340, and it's one less hard-to-hand-solder (often QFN) chip to place. Want the classic UART anyway? UART0 (RXD0 / TXD0) is still broken out to J3 for an external adapter.
| D1 pin |
|---|
An LED is a diode, and a diode is a poor judge of its own appetite.
Give an LED more voltage than it wants and it pulls more and more current until it cooks itself. So you never connect one straight across a supply: you put a with it to set the current. Here that resistor is 470 Ω, which sets a gentle few milliamps: bright enough to see, easy on the driving it. (The exact Ohm's-law sizing is in the deep-dive below if you're curious.) R5 and R6 do this for the two LEDs: LED1 (red) is the power light: wired +3V3 → R5 → LED1 → GND, so it glows whenever the board has power; LED2 (yellow) is the user light, driven by a pin: IO2 → R6 → LED2 → GND.
| Ref | Part | Role |
|---|---|---|
| LED1 | Red, Vf ≈ 1.8 V | Power indicator |
| LED2 | Yellow, Vf ≈ 2.0 V | User / blink LED |
| R5 R6 | 470 Ω | LED series current-limit |
Each LED gets a series resistor, and watch which way round it goes.
The two long headers, J2 and J3, break the module out to the board edge, so on a breadboard you can reach any pin with a jumper.
There's a way to do this with no skip-list to track: every module pin gets exactly one header position, in the module's own physical pin order, so you copy names straight down and never have to decide which pins to bring out. (The GPIO numbers jump around as you go, that's just how they sit on the package, so follow the table below, not a running count.) The handful of rail positions are convenience rails you add, not module pins: each gets a (GND, +3V3, and a +5V tap to power a breadboard) and joins the rail by name. Every other position gets a matching the module pin's name. A few positions are already on a named net, and they take a moment's thought. You'll spot those next.
One rule for every free pin you label here: steer clear of the strapping pins, GPIO0, 3, 45, 46
Two finishing sweeps before the check: make every ground one net, and flag every pin you mean to leave open.
Two finishing sweeps, both about what ERC can and can't see. Grounds: every GND pin has to land on the same net. The trick makes that painless, but the WROOM module's big pad hides its GND pins, and KiCad auto-joins a hidden power pin to the net of its name, so they tie to GND on their own only because your ground net is named GND. That invisible link is exactly the kind ERC can miss, so you confirm it by eye instead of trusting it. No-connects: a genuinely-open pin reads to ERC as a mistake, identical to one you forgot. A flag is you telling ERC 'I meant this', and that's the whole difference between a clean report and a screen of warnings you learn to scroll past.
Ground everything to one net, confirm the hidden pins, then flag every pin you meant to leave open.
Check yourself
You leave a dozen unused module pins unwired and skip the no-connect flags. What does ERC give you?
You can't instruct your way out of every slip. A careful builder with the rule right in front of them still half-finishes a both-ends task across 40 pins: that's just how humans handle long, two-sided work. So the durable move is to design the safety net and learn to read it. That's why this lesson pairs each error-prone step with its ERC tell: label both ends, and if you miss one, ERC flags the loose pin. That flag IS your check. Work the list to zero and the net has done its job; it catches what your eyes skipped.
Trace the things ERC can't see against the answer key, then run the checker.
ERC checks connectivity, not intent. Before your final ERC run, trace these three by eye against the answer-key image just above. They are exactly the slips a green ERC won't save you from.
U2's VIN sits on +5V (after the fuse), not raw VBUS.
Each LED's bar/flat side (K) faces GND.
USB_D+ and USB_D- aren't swapped through D1.
Now let KiCad check it, fix to zero, and export the report the gate wants.
Before you trust the schematic, let KiCad check it: Inspect → Electrical Rules Checker.
reads your whole schematic and flags what's electrically wrong: a pin connected to nothing, two outputs fighting each other, a power rail that nothing drives. Run it, then work the list down to zero. The bar is the same one you'll meet again at DRC: clean, or every remaining flag is an exception you've marked and understood, not one you scrolled past.
| ERC says… | …you do |
|---|---|
| Input power pin not driven | Drop a PWR_FLAG on each rail no chip output drives: VBUS (from the connector), +5V (after the passive fuse), and GND. It tells ERC real power enters there. You don't need one on +3V3: the regulator's output already counts as a driver. Fix it this way; don't ignore it. |
| Pin not connected | Meant to leave it open? Drop a no-connect flag (Q) on it. Now it reads as intentional, not an oversight. |
| Unconnected wire / net | A real mistake: join it, or delete the stray end. Don't scroll past this one. |
ERC checks by pin type: it wants every power-input pin (like the ESP32's 3V3) fed by a power-output pin somewhere. Your +3V3 is fine: the 's output pin counts as a driver, so ERC stays quiet. But VBUS arrives from a connector that has no 'output' pin at all, and +5V sits on the far side of a passive fuse: neither has a chip output behind it, so ERC warns 'input power pin not driven.' A is a tiny symbol whose single pin IS a power-output: drop it on VBUS, +5V, and GND and you've told ERC, truthfully, that real power enters there. That's the honest way to clear the warning, not a mute button. One trap: if you spot GNDPWR in the symbol picker, that's not this: it's a separate stacked-ground symbol that makes its own net; use a plain PWR_FLAG on a normal GND, never GNDPWR.
A clean ERC report is what this stage's gate wants: backed by a readable schematic you keep.
Checkpoint
Quick check: schematic
3/8
You've now read every part on the board and why it's there, captured it as a schematic, and run ERC until it's clean. Attach the ERC report (the gate below tracks it). Carry one thing forward: U1 has a PCB antenna, so when you reach LAYOUT the keep-out underneath it is a hard constraint, not a suggestion.
Next · LAYOUT
Block out the whole sheet before the wiring gets dense: place each sub-circuit as a group so the drawing reads power-in-left, signal left → right, breakout-right, matching the answer-key image at the end of this card. Rough is fine, you're setting reading order, not final placement (that's LAYOUT).
Two habits make this painless. Drag a part to empty space, wire its little sub-circuit there, then slide the finished island into position (it beats fighting auto-placement), and Ctrl+F jumps you straight to any refdes. (Tying two adjacent pins directly, U2 EN to VIN, is fine too; same net, less clutter.)
One finishing habit: keep each part's reference and value from overlapping the symbol, its pins, or a wire, and when a label's in the way, move it into open space. Never declutter by hiding a refdes: the BOM, the layout, and future-you all key off it. That's really the only placement rule that matters here; the rest is taste. (KiCad's own conventions, linked below, spell out the few that are genuinely rules, like power-input pins on the left, outputs on the right.)
Check yourself
In plain terms, why use a regulator (U2) instead of just resistors to drop the voltage?
The RT9080's dropout, the headroom it needs above 3.3 V to keep regulating, is small: about 0.31 V typical, 0.53 V worst-case at this load. So even when USB sags to ~4.6 V under load, the worst case still leaves 4.6 − 0.53 = 4.07 V, comfortably above 3.3 V. A cheaper regulator that needs 1–2 V of headroom would drop out right here and the 3.3 V rail would collapse. That margin is the whole reason we chose a (LDO) part.
Don't treat C5/C6 as optional.
An LDO without its output capacitor can oscillate. That turns your clean rail into noise.
Check yourself
In one line, what do C2/C3 do?
A capacitor only helps if it's close: the longer the trace between it and the pin, the more its help fades (trace inductance gets in the way). Two 0.1 µF caps right at the module's 3V3 pin beat a single 0.2 µF cap sitting a few millimetres away: being close matters more than raw capacitance. The 10 µF (C1) then handles the slower, larger swings the little ones can't.
Still keep C1/C2/C3 tight to the 3V3 pin, it's the habit every board rewards.
But the WROOM gives you a cushion: it already carries decoupling right at the chip inside the module, so these board caps are the bulk reservoir and rail steadier, not the chip's last line for fast current. On a bare chip, a later lesson, that last millimetre is the whole game. Carry the habit into LAYOUT.
| Pull-ups on EN / GPIO0 |
| SW1 SW2 | B3F-1000 | EN (reset) / BOOT (download) |
| C7 | 1 µF | EN reset RC: ~10 ms rise delay + SW1 debounce |
Two pull-ups set the resting level; two buttons override it.
Check yourself
If R1 weren't there and you pressed nothing, what would the EN pin read?
A pull-up only has to set the resting level, not power anything, so it should be 'weak,' meaning a high value. At 3.3 V, a 10 kΩ pull-up leaks just 0.33 mA (3.3 V ÷ 10 kΩ), which is negligible, yet it still firmly holds the pin high. A 100 Ω pull-up would burn 33 mA doing the same job and would fight the button when you press it. Weaker is better here.
+5V| Ref | Part | Role |
|---|---|---|
| F1 | 1206L050YR | Resettable PTC: 0.5 A hold / 1 A trip on VBUS |
| D1 | USBLC6-2SC6 | ESD clamp on D+ / D− and VBUS |
Each I/O line lands on two pins (same node, route-through), and the array is symmetric, so making I/O1 the D+ side is a free choice. D1's VBUS pin sits on the **raw VBUS** rail: ESD belongs at the port, ahead of the fuse.
Power in through the fuse, the CC sink to ground, ESD at the port.
Check yourself
What two things does the USB port need protecting from?
F1 is a : where a glass fuse blows once and needs desoldering, the PTC heats up on overcurrent, throttles the current, then heals when it cools: an accidental short is self-recovering. D1 works at the other end of the timescale: a static spike is over in nanoseconds, so the clamp has to react faster than that, and it has to be low-capacitance, because anything bulky sitting across the high-speed data lines would round off the USB edges and corrupt the signal.
The missing-Rd trap: works on one cable, dead on another The sneaky failure mode to file away: leave R3/R4 off and the board still works on an old USB-A-to-C cable: a USB-A port always has 5 V live, no handshake required.
So a missing sink resistor can look perfectly fine on the cable in your drawer and stone dead on a new USB-C charger. That's the worst kind of bug, intermittent by cable, not by board, and it's why the CC resistors are worth understanding, not just copying.
| Name |
|---|
| Wire to |
|---|
| 1, 6 | I/O1 | USB_D+ |
| 3, 4 | I/O2 | USB_D- |
| 2 | GND | GND |
| 5 | VBUS | VBUS |
Labels first: name the two data nets, then drop those names on every pin they touch. Same name = same net, so the connector, D1, and the module join up with nothing dragged across the sheet.
Nothing else on the schematic says these two wires are a matched team. The names are the instruction that follows them into LAYOUT.
KiCad reads a shared base name plus a paired suffix (+/-, or _P/_N, never mixed) as a differential pair, and that schematic-side naming is what unlocks the diff-pair router and length-matching when you reach LAYOUT. (USB is a 90 Ω pair that wants matched, length-tuned traces, but that's a LAYOUT job; here you just name it right.)
Check yourself
Why label the data nets USB_D+ / USB_D- instead of IO19 / IO20?
Why IO2 for LED2? It's a plain GPIO with no special start-up duty: exactly what you want for something you switch on and off. The pins to keep off a driven part like this are the strapping pins (0, 3, 45, 46), the two USB data pins (19, 20), and the serial-console pins (43, 44, leave those free for debugging). IO2 sits clear of all of them.
Check yourself
You wire the user LED to GPIO0 by mistake. What might go wrong?
The resistor sets the current from the leftover voltage: I = (Vsupply − Vf) ÷ R. The red LED drops about 1.8 V across itself (its ), so on 3.3 V through 470 Ω: (3.3 − 1.8) ÷ 470 ≈ 3.2 mA, bright enough to see, easy on the GPIO. The yellow LED's Vf is higher (~2.0 V), so the same 470 Ω gives a bit less: (3.3 − 2.0) ÷ 470 ≈ 2.8 mA. That's why swapping LED colours at a fixed resistor quietly changes the brightness.
An LED without its series resistor is a short circuit with extra steps: it flashes once and dies.
R5/R6 are not optional.
Every sub-circuit that touches U1 is done: power and ground, EN and IO0, the USB pair, and the user LED all carry their names on the module. Before the headers fan the rest of the module out to the board edge, take one pass down U1 itself and give every remaining GPIO its own net label, so the module is fully named.
Name the module's own nets before you copy them across to the headers. The pins with a dedicated circuit are already labelled; the rest of U1's GPIO are still bare.
| J2 | carries | J3 | carries |
|---|---|---|---|
| 1 | GND | 1 | IO21 |
| 2 | +3V3 | 2 | IO47 |
| 3 | EN ⚠ | 3 | IO48 |
| 4 | IO4 | 4 | IO45 |
| 5 | IO5 | 5 | IO0 ⚠ |
| 6 | IO6 | 6 | IO35 |
| 7 | IO7 | 7 | IO36 |
| 8 | IO15 | 8 | IO37 |
| 9 | IO16 | 9 | IO38 |
| 10 | IO17 | 10 | IO39 |
| 11 | IO18 | 11 | IO40 |
| 12 | IO8 | 12 | IO41 |
| 13 | USB_D- ⚠ | 13 | IO42 |
| 14 | USB_D+ ⚠ | 14 | RXD0 |
| 15 | IO3 | 15 | TXD0 |
| 16 | IO46 | 16 | IO2 ⚠ |
| 17 | IO9 | 17 | IO1 |
| 18 | IO10 | 18 | GND |
| 19 | IO11 | 19 | +5V |
| 20 | IO12 | 20 | GND |
| 21 | IO13 | 21 | +3V3 |
| 22 | IO14 | 22 | GND |
Five positions in that table already carry a named net from a circuit you built earlier: wiring them means reusing that name, not inventing one. They're the ones marked ⚠. Before you read on, try to name them yourself: which earlier island already put each on a net? We confirm all five just below.
There are five ⚠ pins, and you've met every one already. Two are the USB data nets: J2.13 / J2.14 are USB_D- / USB_D+ (they live on IO19 / IO20), label them USB_D- / USB_D+, not IO19/IO20, or you trip a conflicting-label warning. The other three, **J2.3 EN, J3.5 IO0, J3.16 IO2*, already carry a button or the LED on the module side: put the label on that existing node and* on the header pin. The rail positions (GND, +3V3, +5V) get a power symbol; every other position is a plain net label that matches the module pin.
Heads-up: this island breaks the 'every island is the same moves' rhythm. You're not wiring a sub-circuit here: you're carefully transcribing 44 pins against the table above, and the only real trap is miscopying. So slow down. Do J2's first three by hand to find the groove, then work steadily down the table, checking each one, not racing.
ERC catches a missing label (a loose pin).
It can't catch a wrong one: mislabel an end (say IO5 on the module, IO6 at the header) and both nets read 'used,' so ERC stays silent. Check the header against the reference image, not a green ✓.
One habit makes the whole march safe: label both ends of every net: the module pin and its header pin, the same name. For the ⚠ nets (EN, IO0, IO2) the module side already has its label from its own circuit; you just add the matching one at the header. Now the catch ERC only half-covers: miss an end and ERC flags the orphaned pin: the safety net working. But mislabel an end, IO5 on the module, IO6 at the header, and both nets look 'used,' so ERC stays quiet. The header order is the one place to check your work against the reference image (the answer key at the end of this card), not just trust a green ERC.
Two bare loops with nothing else attached: somewhere to clip a meter probe when you first power the board up.
