Place parts and route copper; placement decides if it boots.
Read this once with KiCad closed. The board is four layers, and the two inside are solid ground: get that and half of layout takes care of itself. As you go: Do · = do this in KiCad, Check yourself = a quick gut-check, Eyeball it · = verify by eye.
Layout is where the schematic meets physics. The very same circuit can work flawlessly or barely boot, depending on where the parts sit and how the copper flows between them. You'll do it in five moves: set up the board to your fab's rules, place the parts, route the copper, pour the ground, then confirm it, eyeball what the checker can't catch, then run DRC and export the report. The first move is the one beginners skip and pros never do: you tell KiCad what your factory can build before you route, so every trace is manufacturable from the start: you never route the whole board and then tear it up because a clearance was illegal.
Before anything else, know your canvas: this is a four-layer board, and the two inside layers do one big job.
A bare board here is four sheets of copper stacked with insulation between them. You route signals on the two outside layers, near the parts; the two inside layers are each a solid , unbroken sheets of GND. Those planes are the return path every signal needs. Current always flows in a loop, out along your trace, back through ground, and a solid plane against each signal layer gives that return the shortest, lowest- way home. It's why works and why the USB pair stays clean. Signals on the outside, ground on the inside, so every signal layer hugs a plane. Get that and the rest of the board nearly falls into place. One more way to picture it: on a two-layer board your signals and all their ground returns fight over the same two sheets, a traffic jam that forces long detours; handing the two inner layers entirely to ground is like adding dedicated roads underneath, so every signal up top gets a clear run over solid ground.
Check yourself
Why give up two whole layers to ground?
It's tempting to think a signal is just the trace going out. But current can't go anywhere without a way back: every signal travels in a loop, out on the trace and home through ground. A solid ground plane lets that return current flow directly underneath the trace, for the smallest possible loop. Small loop → low inductance → a clean signal and a rail that doesn't sag. Break the plane (a slot, a gap, a crowd of vias) and the return has to detour around it, the loop balloons, and you get the exact droop and noise the plane was there to prevent. So the single most useful habit in layout is to keep those ground planes unbroken under your signals. Four layers makes that easy: with a solid plane on each inside layer, a signal on either outside layer always has one right against it.
From here your hands are on KiCad. First get the board on screen and framed, then tell KiCad your fab's rules, before you route a single trace.
Your schematic becomes a layout in one step: there's no new download.
Update PCB from Schematic is the one step that turns your finished schematic into a board. It drops every footprint onto the canvas in a loose pile, joined by thin ratsnest lines showing which pads still need connecting. That ratsnest is your to-do list: layout is finished when every one of those lines has become a trace or has been swallowed by the ground pour.
Caution
Do this before you route, or you will redo it
Load your factory's limits into KiCad now, before the first trace: from then on it won't let you draw one PCBWay can't build.
Every board house has limits: the thinnest trace they can etch, the smallest gap, the smallest hole. PCBWay (where this course builds) is no exception, and it publishes those limits as a rules file you load into KiCad so that, from the first trace, it won't let you draw one PCBWay can't build. So you'll load PCBWay's full rules file first, then confirm your starter already carries a matching hand-solder-friendly floor and net classes underneath it, set to sit inside PCBWay's limits (a quick confirm, not typing). From then on KiCad enforces the rules live: it flags a too-tight gap the moment you create it, not after the whole board is routed.
Open the project, not just the board. Net classes and design rules live at the project level, so opening a bare .kicad_pcb on its own quietly loses them. Keep the starter's files together and open it through the project.
Placement is most of the battle: a good floor plan makes the copper almost draw itself. Place everything before you route anything.
the KiCad 10 PCB-editor keys
A few keys do most of the work: hover and press. (See them all: Help ▸ List Hotkeys. Change them in Preferences ▸ Hotkeys.)
| Key | What it does |
|---|---|
| T | Get & Move Footprint: type any refdes and that part jumps to your cursor. No hunting for anything in the PCB editor. |
| X | Route a track |
| V | Drop a via mid-route (switch layers) |
| M / R / D | Move / rotate / drag a part (D keeps tracks attached) |
| B | Fill all copper zones (the pour) |
| E | Edit properties (track width, via size, zone net) |
Two tricks that make placement far easier to see. In the Layers tab of the Appearance panel (right side), turn off F.Fab and F.Mask: that hides the fab-note and solder-mask layers so the canvas shows just pads, silk, and ratsnest. And as you drop each part, you can grab its silkscreen reference designator (the U1 / C2 label), drag it clear of the part, and rotate it with R so it stays readable: the refdes moves independently of the footprint.
Routing is easy when the parts sit in sensible places and miserable when they don't. Place first.
Spend your first real effort on placement, not routing: a good floor plan makes the copper almost draw itself. Two rules carry it. First, connectors live on the edges: the USB-C port (J1) at the bottom short edge where a plug can reach it, and the J2/J3 breakout headers down the two long sides where a breadboard can. Second, place by the same sub-circuit islands you drew in the schematic: U1 as the hub near the top with its antenna overhanging the top edge, the regulator cluster (U2/F1/C5/C6) near where power comes in by the USB port, the decoupling caps close to U1's power pins, boot/reset by their buttons. Anchor U1 first, then build each island outward from it. Parts you place as a tidy group route as a tidy group.
Placement is most of the battle. Your four anchors (U1, J1, J2, J3) are already pinned at their coordinates from the setup step, so the fixed points are set: now place everything else around them, working outside-in.
Check yourself
Why place every part before routing any trace?
Caution
The one mistake you cannot fix later
U1's antenna only works over empty board, and this is the one mistake you can't fix later.
The WROOM module radiates from a printed antenna at one end, and it only works over empty board. Under and around it you keep an : no copper, no , no traces, and no silkscreen either (even ink detunes it). Espressif's own rule is to put the antenna off the board, feed point right at the edge: so place U1 with its antenna end overhanging the top edge. Every castellated pad still lands on the board (none sit on the antenna edge), so only the antenna hangs over; then fence the on-board strip from the edge in to U1's first pads as a rule area (the Draw-it below). Don't lean on the checker to remember this: DRC won't flag a missing keep-out unless you've drawn that rule area. It's the headline review item, and the one mistake you can't fix without spinning a whole new board.
Remember C2/C3, the 3V3 bypass caps? Their whole value is decided here, by where you place them.
A does its best work parked close to the pin it feeds, with a short, fat path to ground. On a bare chip you'd jam C2/C3 hard against the power pins and fight for every millimetre. On the WROOM you can't, and don't need to: its pads are castellations tucked under the module body (nothing on top to sit a cap on), and it carries its own bypass caps inside, on the die, so the fast, loop-sensitive job is already handled better than any external cap could. Your C1/C2/C3 do the slower tier, bulk energy and mid-frequency, which isn't loop-sensitive. So place C2 and C3 in open board just off U1's 3V3 side, each with a ground via at its own pad so the return drops straight into the plane, and put C1, the , near where power enters. Get them reasonably near, but never distort the board chasing pads you can't reach. Carry the at-the-pin instinct into a later bare-chip board, where that last millimetre is the whole game.
Hands on the router: order matters more than precision here.
Routing four layers raises two questions you have to keep straight: which layer am I on, and where does this via come out?
Routing four coppers turns on two controls you'll use constantly. First, the active layer: click a layer's name in the Appearance panel (right side) to route on it. Starting a track from a pad drops you onto that pad's layer automatically, so you rarely pick by hand. F.Cu shows red, B.Cu blue, and your two inner planes carry their own colours.
Second, where a via comes out. Pressing V drops a through via and jumps you to the next layer in the active layer pair, so set that pair before you route: Route ▸ Set Layer Pair, and choose F.Cu / B.Cu. That's the hop you want, top straight to bottom: In1.Cu and In2.Cu are solid ground, and you keep signals off them. When you want a via to land somewhere specific instead, press < (Select Layer and Place Through Via) and pick the target layer from the dialog.
One habit worth building:
D+ and D− are a team: route them as one, with the tool the schematic naming unlocked.
USB D+ and D− are a : the receiver reads the difference between them, so they must travel together, side by side, the same length, over unbroken ground. Because you named the nets USB_D+ / USB_D- back in the schematic, KiCad's differential-pair router already knows they're a pair. Reach it with hotkey 6, or click and hold the route button in the right toolbar until its palette opens and pick Route Differential Pairs. It lays both traces at once, correctly spaced, with the width and gap taken from the net class (DP Width and DP Gap, already set in your starter).
Route the whole pair before you touch another trace, start to finish. It begins at J1, which brings each data line out
The pair is down. Now the rest, in the order that matters: power first, then the remaining signals. Ground you don't route at all: it comes last, as the pour.
Net classes auto-set the width: nothing to pick. Order matters more than precision here.
Route in the order power actually flows: from where it enters (J1) to where it's used (U1). Each net below is one move, and the gotcha rides with it.
You just fanned the GPIO out to the headers, and the USB pair taps out there too: J2.13 and J2.14 carry USB_D- and USB_D+, which hangs a small stub off a live . At the wrong speed that would be reckless. Stubs only reflect enough to matter at USB high-speed (480 Mbit/s), where the edges are fast enough to notice a few millimetres of copper. At full-speed's slow edges a few-millimetre stub is electrically invisible, so exposing the native-USB pins for access costs you nothing here. The same tap on a 480 Mbit/s board would be a real problem.
One detail the four-layer stackup adds: those header pins are
Hands on: flood the planes and tie everything to them.
Now make the ground planes real, and tie everything to them.
You routed power and signals and left every GND pad open; now you make ground real. Fill In1.Cu and In2.Cu as zones assigned to GND: those two inside layers are the board's ground. Add GND pours on the top and bottom layers too, around the parts, and tie all four together with a scatter of so the ground reads as one continuous body. Two ties matter most: drop vias under U1's centre pad (its main ground and heat path, straight into the planes), and keep a via next to each decoupling cap. The one place the copper must stop is the antenna keep-out: your rule area already excludes it on every layer.
One pour, one keep-out exclusion, one scatter of vias.
A here is a plain through via: a plated barrel from F.Cu
Hands on: name every header pin on the back silk.
A breakout is only useful if you can tell the pins apart. The top silk is packed with the module and parts, so the pin labels go on the back (B.Silkscreen), with mirror ticked so they read the right way round.
One last silk touch before you check it. Real boards carry a version marker so a physical board traces back to the exact design it was built from, and this one is yours to sign.
Before you run the checker, trace by eye the things it's blind to: the four that actually make this board work. Compare against the answer key.
Same move as the schematic: the checker is blind to intent. DRC checks clearances, widths and drills, and none of these. The gate makes you tick them off before it accepts your upload.
The antenna keep-out is genuinely empty on every layer.
Each decoupling cap really is at its pin, with a ground via.
The USB pair is matched and runs over the unbroken inner ground plane the whole way.
U1's centre pad is stitched to ground.
Let KiCad check it against your fab's rules.
You set your fab's rules up front and routed inside them, so this is the final confirmation, not a surprise.
Run Inspect ▸ Design Rules Checker. Read two tabs, not one: Violations and Unconnected Items. Both want to read 0. Because your fab's rules have been switched on since Board Setup, a board you routed carefully comes up clean or close to it: what it flags now is usually a ratsnest line you never finished or a clearance you nudged tight. Clear the errors to zero (harmless warnings, like silk over a pad, are fine to leave):
| DRC says… | …you do |
|---|---|
| Clearance violation | Two coppers too close: nudge a trace or part apart. |
| Track / via too small | Widen the track, or grow the via past its minimum. |
| Unconnected items | A ratsnest line you never routed: finish it (or No-Connect it on purpose). |
| Courtyard overlap | Two parts physically clash: move one. |
The final confirmation, not a surprise: your fab's rules have been on the whole time.
| Rule | What it means | PCBWay's floor |
|---|
| Min track width | The thinnest copper trace PCBWay can reliably etch. | 0.15 mm |
| Min clearance | Smallest gap between two coppers before they risk shorting. | 0.15 mm |
| Min hole / drill | Smallest hole their drill makes (smaller than this costs extra). | 0.3 mm |
| Min annular ring | The copper collar around a hole that must survive a slightly-off drill. | 0.15 mm |
Their complete rule set, loaded once, then KiCad enforces it live.
Two screens of Board Setup, both already filled in by your starter: the fab's floor, and the per-net widths. You're confirming here, not typing.
Reopen Board Setup ▸ Design Rules ▸ Custom Rules. Your final DRC at the end is the last proof.
PCBWay's rule text fills the panel.
Check yourself
Why set the rules before routing instead of checking at the end?
Rules loaded, now the board itself: draw the outline, then pin the four parts that must sit at exact coordinates.
UNDER THE ANTENNA
The ground pour (hatch) fills the rest, under the U1 body and pads.
drag to rotate
Draw the keep-out now, before you route or pour: a rule area added late is one the copper has already crept past.
Open the rule area's properties and check both halves of the dialog.
Under Layers: all four copper layers (F.Cu, In1.Cu, In2.Cu, B.Cu) and both silkscreens are ticked.
Under Keepouts: tracks, vias, pads and zone fills are all on.
Check yourself
You pour ground everywhere for a clean return path. Why must it stop short of U1's antenna?
The WROOM's printed antenna is tuned to radiate at 2.4 GHz: its shape and its surroundings are designed for exactly that frequency. Bring copper close (a , a trace, even thick silkscreen) and you add stray capacitance that shifts the tuning, like detuning a guitar string by hanging a weight on it. The antenna still 'works,' but its sweet spot slides off 2.4 GHz and most of your transmit power reflects back into the chip instead of leaving the board: range drops from across-the-house to across-the-desk. No firmware setting recovers it; the only cure is keeping the keep-out genuinely empty, which is why the module is usually placed hanging off the board edge.
✓ cap right at the pin
Short path, low inductance; the cap dumps current fast.
✗ cap far from the pin
Long path, trace inductance; chokes the fast current.
Check yourself
A decoupling cap is electrically correct in the schematic but placed 15 mm from the pin. Does it still work?
When the ESP32 suddenly demands current, that current flows out of the , into the pin, and back through ground: a little loop. Every loop of conductor has inductance, and inductance fights sudden changes in current: the voltage it costs you is V = L × (di/dt). The chip's demand changes incredibly fast, a big di/dt, so even a few nanohenries of trace inductance becomes a real voltage dip right at the pin, exactly when the chip needs the rail to hold steady. The fix is pure geometry: a shorter, fatter path from cap to pin to ground makes a smaller loop, which means less inductance and less droop. So 'close to the pin' isn't a nicety. It's the whole mechanism.
Two filled planes will bury your traces. Three switches dig them back out. Layer Display Options (Appearance panel) dims or hides the layers you're not routing on. Show only zone boundaries (left toolbar) hides the pour fills while leaving them filled: hiding a fill is not the same as unfilling it. And the Selection Filter, under the Appearance panel, stops you grabbing a zone every time you reach for a track.
Routing is the fiddliest part of the build. Here's what separates a clean board from a rat's nest. The golden rule here: signals on the two outside layers, solid ground on the two inside. Almost everything below is just protecting those planes.
| Trap | Do this instead |
|---|---|
| Routing a signal on an inner layer | In1.Cu and In2.Cu are solid ground. Keep signals on the two outside layers (F.Cu, B.Cu); a trace on an inner plane cuts a slot the return current must detour around. |
| Sharp 90° corners (kinks) | Route in 45° bends (KiCad's default). Acute angles can trap etchant, and 45° is tidier and shorter. 90° does not 'reflect' at this speed (see the deep-dive). |
| Crossing another net on one layer | You can't share a layer. Move ONE trace to the bottom (B.Cu is a full signal layer with a ground plane under it) with a via, then reroute or come back up. On four layers the bottom is fair game for crossings. |
| A via dropped inside a pad | Keep vias out of pads; they wick your solder away when you hand-solder. Put the via just beside the pad on a short stub. |
| Routing across the antenna keep-out | Never. Route around it. No copper in that zone, ever. |
| A long, wandering signal path | The return flows in the plane right against the trace, so a wandering signal drags a big return loop. Keep signals fairly direct. |
You'll hear that 90° trace corners cause reflections and wreck signals. For almost anything you'll build, and certainly at this board's speeds, that's a myth. The reflection story only bites at multi-GHz edge rates on long, controlled-impedance lines. The kernel of truth is older: back in the acid-etch days a sharp acute inside angle (sharper than 90°) could trap etchant and over-etch a notch, or leave an 'acid trap' sliver. A 90° corner isn't acute, so even that barely applies. So why route 45°? Three honest reasons: it's a hair shorter, it looks clean and professional, and it stops you ever drawing an accidental acute angle. KiCad routes 45° by default: let it, and don't lose sleep over a 90° corner on a GPIO trace.
A6B6USB_D+A7B7USB_D-IO19IO20USB_D-USB_D+Do the whole pair here, start to finish, before any other trace. The diff-pair router lays the coupled run; the plain router does the J1 twin-ties. Do it once and the rest is muscle memory.
When you tie D1's ground pad into the planes, the via KiCad drops takes the wide Power-class size (1.0 mm).
In the cramped ESD area that via plus its clearance blocks the pair from leaving D1, so it won't route. Fix: shrink that one via. Fastest, with the via selected, pick the 0.8 / 0.4 mm via from the via-size dropdown in the top toolbar (your starter ships three presets: 1.0, 0.8 and 0.6 mm); or press E and type the sizes. 0.8 mm is enough, and it is what the reference board uses; 0.6 / 0.3 mm is the fab floor if you ever want more room. Your stitching vias out in open copper stay big. Only this cramped one shrinks.
Check yourself
Why route USB D+ and D− together, matched, and over unbroken ground?
USB full-speed runs at 12 Mbit/s with slow edges, so the signal is forgiving. A two-layer board with a broken ground under the pair would very likely still enumerate and run. We went to four layers for a different reason: routing.
On this board the USB-C connector sits at one edge and the module's native-USB pins (IO19/IO20) are fixed at the opposite corner, so D+ and D- run a long diagonal clear across the board. Keeping an unbroken ground directly under that whole run, while every GPIO also fans out to the headers, fought us through the entire layout. Every GPIO that crossed under it punched another hole in the pair's return path.
Four layers buys a dedicated inner right under the pair. The pair rides the top over that one continuous reference the whole way, no matter what the other layers carry. The idea generalizes: the routing can force more layers than the signal speed alone would call for. A short pair in a clear corner stays two layers happily. A long pair boxed in by fixed parts earns the upgrade.
B.CuIn1.CuIn2.CuGNDF.CuIn1.CuIn2.CuB.CuIn1.CuIn2.CuCheck yourself
You poured solid ground planes but forgot to stitch vias under U1's centre pad. What's wrong?
Flood two whole layers with copper and every GND pad should become impossible to heat: the plane would wick your iron's heat away as fast as you deliver it. KiCad handles this for you. When a zone fills around a pad on its own net, it connects through thermal reliefs instead of solid copper: a few thin spokes that carry the current but throttle the heat path, so the pad still climbs to temperature under an iron. Fill the zones and you can see them, little wagon-wheel spokes around each GND pad. This is why a poured board is still hand-solderable at all, and it's why the design rules carry a minimum spoke count. The exception is a big thermal pad like U1's centre, which meets the plane through its via cluster and wants real preheat rather than a hopeful iron.
Run DRC on a finished board and you'll usually still see a handful of flags. That's normal: DRC reports errors and warnings together, but they aren't the same thing. An error is something the fab genuinely can't make, or that breaks the circuit: two coppers too close, a trace thinner than the process allows, a hole below the drill minimum, a net left unrouted. Those must reach zero. A warning is cosmetic: silkscreen clipped by the board edge, a reference label brushing a pad, two part outlines just touching. None of it changes the copper or the build, so the gate (and the fab) ignore warnings, and you can leave them. The discipline: read every flag once so you know which bucket it's in, drive the errors to zero, and don't sweat the warnings.
Checkpoint
Quick check: layout
4/8
Your board is routed and DRC-clean against your fab's rules. Pass the check below to clear this stage. Next, the DRC & Gerbers stage runs one last DRC, takes your clean DRC report, and exports the files the factory builds from, which you inspect before you order.
Next · DRC + GERBER